LM3S101_0610 Datasheet, PDF (26/300 Pages) List of Unclassifed Manufacturers – Microcontroller

Architectural Overview
1.5
System Block Diagram
Figure 1-2. LM3S101 Controller System-Level Block Diagram
VDD_3.3V
LDO
LDO
VDD_2.5V
GND
ARM Cortex-M3
(20 MHz)
CM3Core
NVIC
DCode
ICode
Flash
(8 KB)
Debug Bus
OSC0
OSC1
RST
IOSC PLL
POR
BOR
System
Control
& Clocks
GPIO Port A
APB Bridge
SRAM
(2 KB)
Watchdog
Timer
GPIO Port B
PA5/SSITx
PA4/SSIRx
PA3/SSIFss
PA2/SSIClk
PA1/U0Tx
PA0/U0Rx
SSI
UART0
GPIO Port C
Analog
Comparators
GP Timer1
GP Timer0
PC3/TDO/SWO
PC2/TDI
PC1/TMS/SWDIO
PC0/TCK/SWCLK
LM3S101
JTAG
SWD/SWO
PB7/TRST
PB6/C0+
PB5/C0o/C1-
PB4/C0-
PB3
PB2
PB1/32KHz
PB0/CCP0
26
October 5, 2006
Preliminary