LM3S2016 Datasheet, PDF (437/468 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2016 Microcontroller
19.2.3
19.2.4
Parameter Name
Temperature stability (0 - 85 °C) ±25
Motional capacitance (typ)
27.8
Motional inductance (typ)
14.3
Equivalent series resistance (max) 120
Shunt capacitance (max)
10
Load capacitance (typ)
16
Drive level (typ)
100
Value
±25 ±25
37.0 55.6
19.1 28.6
160 200
10
10
16
16
100 100
Units
±25 ppm
63.5 pF
32.7 mH
220 Ω
10
pF
16
pF
100 µW
Analog-to-Digital Converter
Table 19-9. ADC Characteristics
Parameter Parameter Name
Min Nom Max Unit
V_ADCIN
Maximum single-ended, full-scale analog input voltage -
Minimum single-ended, full-scale analog input voltage -
- 3.0 V
- 0V
Maximum differential, full-scale analog input voltage - - 1.5 V
Minimum differential, full-scale analog input voltage
- - -1.5 V
C_ADCIN
Equivalent input capacitance
- 1 - pF
N
Resolution
- 10 - bits
f_ADC
ADC internal clock frequency
t_ADCCONV Conversion time
7 8 9 MHz
-
- 16 t_ADCcycles^a
f _ADCCONV Conversion rate
438 500 563 k samples/s
INL
Integral nonlinearity
- - ±1 LSB
DNL
Differential nonlinearity
- - ±1 LSB
OFF
GAIN
Offset
Gain
- - ±1 LSB
- - ±1 LSB
a. t_ADC= 1/f_{ADC clock}
I²C
Table 19-10. I²C Characteristics
Parameter No. Parameter Parameter Name
Min Nom Max
Unit
I1^a
t_SCH Start condition hold time
36 -
-
system clocks
I2^a
t_LP
Clock Low period
36 -
-
system clocks
I3^b
t_SRT I2CSCL/I2CSDA rise time (V_IL =0.5 V to V _IH =2.4 V) - - (see note b)
ns
I4^a
t_DH Data hold time
2-
-
system clocks
I5^c
t_SFT I2CSCL/I2CSDA fall time (V_IH =2.4 V to V _IL =0.5 V) - 9
10
ns
I6^a
t_HT Clock High time
24 -
-
system clocks
I7^a
t_DS Data setup time
18 -
-
system clocks
I8^a
t_SCSR Start condition setup time (for repeated start condition 36 -
-
system clocks
only)
I9^a
t_SCS Stop condition setup time
24 -
-
system clocks
a. Values depend on the value programmed into the TPR bit in the I²C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I ²C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
November 30, 2007
437
Preliminary