LM3S2016 Datasheet, PDF (15/468 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2016 Microcontroller
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 257
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 257
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 258
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 258
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 259
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 259
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 261
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 262
ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 263
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 265
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 273
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 275
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 277
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 279
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 280
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 281
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 282
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 284
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 286
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 288
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 290
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 291
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 292
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 294
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 295
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 296
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 297
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 298
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 299
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 300
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 301
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 302
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 303
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 304
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 305
Synchronous Serial Interface (SSI) ............................................................................................ 306
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 318
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 320
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 322
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 323
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 325
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 326
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 328
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 329
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 330
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 331
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 332
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 333
November 30, 2007
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Preliminary