LM3S2016 Datasheet, PDF (210/468 Pages) List of Unclassifed Manufacturers – Microcontroller

Watchdog Timer
10
10.1
Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way.
The Stellaris^® Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, a locking register, and user-enabled stalling.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
Block Diagram
Figure 10-1. WDT Module Block Diagram
Interrupt
System Clock
Control / Clock /
Interrupt
Generation
WDTCTL
WDTICR
WDTRIS
WDTMIS
WDTLOCK
WDTTEST
WDTLOAD
32-Bit Down
Counter
0x00000000
Comparator
WDTVALUE
Identification Registers
WDTPCellID0
WDTPCellID1
WDTPCellID2
WDTPCellID3
WDTPeriphID0 WDTPeriphID4
WDTPeriphID1 WDTPeriphID5
WDTPeriphID2 WDTPeriphID6
WDTPeriphID3 WDTPeriphID7
10.2
Functional Description
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the
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November 30, 2007
Preliminary