LM3S2016 Datasheet, PDF (14/468 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 202
GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 203
GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 204
GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 205
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 206
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 207
GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 208
GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 209
Watchdog Timer ........................................................................................................................... 210
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 213
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 214
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 215
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 216
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 217
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 218
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 219
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 220
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 221
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 222
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 223
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 224
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 225
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 226
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 227
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 228
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 229
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 230
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 231
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 232
Analog-to-Digital Converter (ADC) ............................................................................................. 233
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 239
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 240
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 241
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 242
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 243
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 244
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 247
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 248
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 249
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 250
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 251
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 253
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 256
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 256
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 256
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 256
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 257
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 257
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November 30, 2007
Preliminary