LM3S2016 Datasheet, PDF (39/468 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2016 Microcontroller
3 Memory Map
The memory map for the LM3S2016 controller is provided in Table 3-1 on page 39.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Important: In Table 3-1 on page 39, addresses not listed are reserved.
Table 3-1. Memory Map^a
Start
End
Memory
0x0000.0000
0x2000.0000
0x2010.0000
0x2200.0000
0x2400.0000
FiRM Peripherals
0x4000.0000
0x4000.4000
0x4000.5000
0x4000.6000
0x4000.7000
0x4000.8000
0x4000.C000
0x4000.D000
Peripherals
0x4002.0000
0x4002.0800
0x4002.4000
0x4002.5000
0x4002.6000
0x4002.7000
0x4003.0000
0x4003.1000
0x4003.8000
0x4004.0000
0x400F.D000
0x400F.E000
0x4200.0000
Private Peripheral Bus
0x0000.FFFF
0x2000.1FFF
0x21FF.FFFF
0x23FF.FFFF
0x3FFF.FFFF
0x4000.0FFF
0x4000.4FFF
0x4000.5FFF
0x4000.6FFF
0x4000.7FFF
0x4000.8FFF
0x4000.CFFF
0x4000.DFFF
0x4002.07FF
0x4002.0FFF
0x4002.4FFF
0x4002.5FFF
0x4002.6FFF
0x4002.7FFF
0x4003.0FFF
0x4003.1FFF
0x4003.8FFF
0x4004.0FFF
0x400F.DFFF
0x400F.EFFF
0x43FF.FFFF
Description
On-chip flash ^b
Bit-banded on-chip SRAM^c
Reserved non-bit-banded SRAM space
Bit-band alias of 0x2000.0000 through 0x200F.FFFF
Reserved non-bit-banded SRAM space
For details on
registers, see
page ...
113
113
-
109
-
Watchdog timer
212
GPIO Port A
139
GPIO Port B
139
GPIO Port C
139
GPIO Port D
139
SSI0
317
UART0
272
UART1
272
I2C Master 0
356
I2C Slave 0
369
GPIO Port E
139
GPIO Port F
139
GPIO Port G
139
GPIO Port H
139
Timer0
185
Timer1
185
ADC
238
CAN0 Controller
391
Flash control
113
System control
61
Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
-
November 30, 2007
39
Preliminary