LM3S2016 Datasheet, PDF (16/468 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 334
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 335
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 336
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 337
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 338
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 339
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 340
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 341
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 342
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 343
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 357
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 358
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 362
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 363
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 364
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 365
I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 366
I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 367
I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 368
I²C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 370
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
I²C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 371
I²C Slave Data (I2CSDR), offset 0x008 ........................................................................... 373
I²C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 374
I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 375
I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 376
Register 16: I²C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 377
Controller Area Network (CAN) Module ..................................................................................... 378
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 392
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 394
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 397
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 398
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 400
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 401
Register 7: CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 403
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 404
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 404
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 405
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 405
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 408
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 408
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 409
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 409
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 410
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 410
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 411
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 411
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 412
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November 30, 2007
Preliminary