LM3S2016 Datasheet, PDF (424/468 Pages) List of Unclassifed Manufacturers – Microcontroller

Signal Tables
Pin Name
ADC1
ADC2
ADC3
CAN0Rx
CAN0Tx
CCP0
CCP1
CCP2
CCP3
CMOD0
CMOD1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDA
GNDA
I2C0SCL
I2C0SDA
LDO
NC
NC
Pin Number
2
5
6
10
11
66
34
67
23
65
76
9
15
21
33
39
45
54
57
63
69
82
87
94
4
97
70
71
7
16
17
Pin Type
I
I
I
I
O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O
I/O
-
-
-
Buffer Type Description
Analog Analog-to-digital converter input 1.
Analog Analog-to-digital converter input 2.
Analog Analog-to-digital converter input 3.
TTL
CAN module 0 receive
TTL
CAN module 0 transmit
TTL
Capture/Compare/PWM 0
TTL
Capture/Compare/PWM 1
TTL
Capture/Compare/PWM 2
TTL
Capture/Compare/PWM 3
TTL
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
TTL
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
OD
I2C module 0 clock
OD
I2C module 0 data
Power
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 µF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
-
No connect
-
No connect
424
November 30, 2007
Preliminary