LM3S2016 Datasheet, PDF (253/468 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2016 Microcontroller
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044
This register contains the configuration information for each sample for a sequence executed with
Sample Sequencer 0. When configuring a sample sequence, the END bit must be set at some point,
whether it be after the first sample, last sample, or any sample in between.
This register is 32-bits wide and contains information for eight possible samples.
ADC Sample Sequence Control 0 (ADCSSCTL0)
Base 0x4003.8000
Offset 0x044
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved IE7
END7
D7 reserved IE6
END6
D6 reserved IE5
END5
D5 reserved IE4
END4
D4
Type RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved IE3
END3
D3 reserved IE2
END2
D2 reserved IE1
END1
D1 reserved IE0
END0
D0
Type RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31
30
29
28
27
Name
reserved
IE7
END7
D7
reserved
Type
RO
R/W
R/W
R/W
RO
Reset
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8th Sample Interrupt Enable
The IE7 bit is used during the eighth sample of the sample sequence
and specifies whether the raw interrupt signal (INR0 bit) is asserted at
the end of the sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to a controller-level interrupt.
When this bit is set, the raw interrupt is asserted, otherwise it is not. It
is legal to have multiple samples within a sequence generate interrupts.
8th Sample is End of Sequence
The END7 bit indicates that this is the last sample of the sequence. It is
possible to end the sequence on any sample position. Samples defined
after the sample containing a set END are not requested for conversion
even though the fields may be non-zero. It is required that software write
the END bit somewhere within the sequence. (Sample Sequencer 3,
which only has a single sample in the sequence, is hardwired to have
the END0 bit set.)
Setting this bit indicates that this sample is the last in the sequence.
8th Sample Diff Input Select
The D7 bit indicates that the analog input is to be differentially sampled.
The corresponding ADCSSMUXx nibble must be set to the pair number
"i", where the paired inputs are "2i and 2i+1". When set, the analog
inputs are differentially sampled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
November 30, 2007
253
Preliminary