MC3610 Datasheet, PDF (23/67 Pages) List of Unclassifed Manufacturers – Axis Accelerometer

MC3610 3-Axis Accelerometer
Preliminary Datasheet
6 INTERRUPTS
6.1 INTERRUPT BLOCK
The interrupt block contains the logic for the sample acquisition, FIFO, WAKE and SNIFF
interrupts. Optionally, an interrupt can trigger an external signal. When Status Register 2 is
read, the interrupt flag register, all pending interrupts will be cleared.
6.2 FLAG BITS AND ENABLES
Interrupts are enabled and disabled using Register 0x17. Interrupt status is read from Register
0x08 and Register 0x09. The INT_PEND (interrupt pending) flag in Register 0x08 is set by the
device if any of the interrupt bits are set in register 0x09. All flags and enable bits are active
high.
6.3 INTERRUPT ON WAKE (INT_WAKE)
Interrupt on WAKE is the primary interrupt used to signal that activity has been detected during
SNIFF, and that a transition to CWAKE is in process. Servicing the INT_WAKE interrupt is not
required, and will not prevent the device from automatically moving to CWAKE mode,
acquiring sample data, and writing it to the FIFO (if enabled). Reading register 0x09 will clear
this interrupt. Register 0x17 bit 3 must be ‘1’ for this interrupt to be enabled.
6.4 INTERRUPT ON SAMPLE (INT_ACQ)
The NEW_DATA flag bit in Register 0x08 bit 3 is always enabled; there is no way to disable it.
The bit is cleared each time register 0x08 is read. This flag generates an interrupt only if the
INT_ACQ bit in Register 0x09 bit 3 is ‘1’. Each new sample generates a new interrupt only if
register 0x09 is read to clear the flag and rearm the interrupt. This interrupt is only active in
CWAKE and TRIG modes. Register 0x17 bit 3 must be ‘1’ for this interrupt to be enabled.
6.5 INTERRUPT ON FIFO EMPTY (INT_FIFO_EMPTY)
The FIFO is always empty following a POR, reset, or FIFO reset condition. After the device
initialized the FIFO_EMPTY flag in register 0x08 bit 4 will be ‘1’. Reading register 0x08 has no
effect on this flag. The INT_FIFO_EMPTY interrupt flag in register 0x09 bit 4 will transition high
each time a new empty condition is detected. For example, if the FIFO is empty and
INT_FIFO_EMPTY at register 0x09 bit 4 is ‘1’, the FIFO empty condition must be negated
(e.g. the FIFO must become ‘not’ empty), and then empty again for the INT_FIFO_EMPTY flag
to retrigger. Internally the FIFO compares the write and read pointers; if they are at the same
address, then the empty condition exists. Register 0x17 bit 4 must be ‘1’ for this interrupt to be
enabled.
6.6 INTERRUPT ON FIFO FULL (INT_FIFO_FULL)
The FIFO_FULL flag at register 0x08 bit 5 is set to ‘1’ when the FIFO contains the maximum of
32 samples. The INT_FIFO_FULL interrupt flag in register 0x09 bit 5 will transition high each
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