CC2510FX Datasheet, PDF (64/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
12.9.8 Flash Programming
Programming of the on-chip flash is
performed via the debug interface. The
external host must initially send
instructions using the DEBUG_INSTR
debug command to perform the flash
programming with the Flash Controller as
described in section 13.16.
12.10 RAM
The CC2510Fx/CC2511Fx contains static
RAM. At power-on the contents of RAM is
undefined. The RAM size is 1, 2 or 4 KB in
total, mapped to the memory range
0xF000 – 0xFFFF. In the F8 and F16
versions parts of this memory range is not
used.
The memory locations 0xFDA2-0xFEFF
consisting of 350 bytes in XDATA memory
that do not retain data when power modes
PM2/3 is entered. All other RAM memory
locations are retained in all power modes.
Refer to Table 28 for a description of the
SRAM memory map.
12.11 Flash Memory
The on-chip flash memory consists of
32768 bytes. The flash memory is
primarily intended to hold program code.
The flash memory has the following
features:
• Flash page erase time: 20 ms
• Flash chip (mass) erase time: 20 ms
• Flash write time (16 bit word): 20 µs
• Data retention⁴:100 years
• Program/erase endurance: Minimum
1,000 cycles
The flash memory consists of the Flash
Main Page which is where the CPU reads
program code and data. The flash memory
also contains a Flash Information Page
which contains the Flash Lock Bits. The
Flash Information Page and hence the
Lock Bits is only accessed by first
selecting this page through the Debug
Interface. The Flash Controller (see
section 13.16) is used to write and erase
the contents of the flash memory.
When the CPU reads instructions from
flash memory, it fetches the next
instruction through a cache. The
instruction cache is provided mainly to
reduce power consumption by reducing
the amount of time the flash memory itself
is accessed. The use of the instruction
cache may be disabled with the
MEMCTR.CACHDIS register bit.
12.12 Memory Arbiter
The CC2510Fx/CC2511Fx includes a memory
arbiter which handles CPU and DMA
access to all memory space.
A control register MEMCTR is used to
control the flash cache. The MEMCTR
register is described below.
4 _{At room temperature}
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 64 of
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