CC2510FX Datasheet, PDF (171/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
13.15.6.2 Double buffering
Double buffering allows two packets to be
buffered in the FIFO. This reduces
retransmission and is highly
recommended for isochronous endpoints
which do not use retransmission. For
isochronous endpoint one data packet will
be sent/received every USB frame.
However, the data packet may be
sent/received at any time during the USB
frame period. Thus, two data packets may
be sent/received at a few micro seconds
interval. For isochronous endpoints an
incoming packet will be lost if there is no
buffer available and a zero length data
packet will be sent if there is no data
packet ready for transmission when the
USB host requests data. Double buffering
is not as critical for bulk and interrupt
endpoints since packets will not be lost.
Double buffering, however, may improve
the effective data rate for bulk endpoints.
To enable double buffering for an IN
endpoint, set USBCSIH.IN_DBL_BUF to
1. To enable double buffering for an OUT
endpoint, set USBCSOH.OUT_DBL_BUF to
1.
13.15.6.3 FIFO Access
The endpoint FIFOs are accessed by
reading and writing to the registers in
Table 53. Writing to a register causes the
byte written to be inserted into the IN
FIFO. Reading a register causes the next
byte in the OUT FIFO to be extracted and
the value of this byte to be returned.
When a data packet has been written to a
IN FIFO the USBCSIL.INPKT_RDY bit
must be set. If double buffering is enabled,
the USBCSIL.INPKT_RDY bit will be
cleared immediately after it has been
written and another data packet can be
loaded. This will not generate an interrupt,
since an interrupt is only generated when
a packet has been sent. When double
buffering is used firmware should check
the status of the USBCSIL.PKT_PRESENT
bit before writing to the IN FIFO. If this bit
is 0, two data packets can be written.
Double buffered isochronous endpoints
should only need to load two packets the
first time the IN FIFO is loaded. After that,
one packet is loaded for every USB frame.
To send a zero length data packet set
USBCSIL.INPKT_RDY without loading a
data packet into the IN FIFO.
A data packet can be read from the OUT
FIFO when the USBCSOL.OUTPKT_RDY
bit is set. An interrupt will be generated
when this occurs, if enabled. The size of
the data packet is kept in the
USBCNTH:USBCNTL registers. When the
data packet has been read from the OUT
FIFO, the USBCSOL.OUTPKT_RDY bit
must be cleared. If double buffering is
enabled there may be two data packets in
the FIFO. If another data packet is ready
when the USBCSOL.OUTPKT_RDY bit is
cleared the USBCSOL.OUTPKT_RDY bit
will be set immediately and an interrupt will
be generated to signal that a new data
packet has been received. The
USBCSOL.FIFO_FULL bit will be set when
there are two data packets in the OUT
FIFO.
The AutoClear feature is supported for
OUT endpoints. When enabled, the
USBCSOL.OUTPKT_RDY bit is cleared
automatically when USBMAXO bytes have
been read from the OUT FIFO. The
AutoClear feature is enabled by setting the
USBCSOH.AUTOCLEAR bit. The AutoClear
feature can be used to reduce the time the
data packet occupies the OUT FIFO buffer
and is typically used for bulk endpoints.
A complementary AutoSet feature is also
supported for IN endpoints. When
enabled, the USBCSIL.INPKT_RDY bit is
set automatically when USBMAXI bytes
have been written to the IN FIFO. The
AutoSet feature is enabled by setting the
USBCSOH.AUTOSET bit. The AutoSet
feature can reduce the overall time it takes
to send a data packet and is typically used
for bulk endpoints.
13.15.6.4 Endpoint Interrupts
IN endpoints generate interrupts by setting
the interrupt flags in the USBIIF register in
the following situations:
• A data packet has been
successfully sent to the host.
• A STALL condition has been
generated by the hardware.
• The IN FIFO is flushed due to the
USBCSIH.FLUSH_PACKET bit
being set.
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 171 of
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