CC2510FX Datasheet, PDF (135/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
13.9 AES Coprocessor
With the CC2510Fx/CC2511Fx, data
encryption can be performed using a
dedicated coprocessor which supports
Advanced Encryption Standard, AES. The
coprocessor allows encryption/decryption
to be performed with minimal CPU usage.
The coprocessor has the following
features:
• ECB, CBC, CFB, OFB, CTR and CBC-
MAC modes.
• Hardware support for CCM mode
• 128-bits key and IV/Nonce
• DMA transfer trigger capability
13.9.1 AES Operation
To encrypt a message, the following
procedure must be followed:
• Load key
• Load initialization vector (IV)
• Download and upload data for
encryption/decryption.
The AES coprocessor works on blocks of
128 bits. A block of data is loaded into the
coprocessor, encryption is performed and
the result must be read out before the next
block can be processed. Before each
block load, a dedicated start command
must be sent to the coprocessor.
13.9.2 Key and IV
Before a key or IV/nonce load starts, an
appropriate load key or IV must be issued
to the coprocessor. When loading the IV it
is important to also set the correct mode.
A key load or IV load operation aborts any
processing that could be running.
The key, once loaded, stays valid until a
key reload takes place.
The IV must be downloaded before the
beginning of each message (not block).
Both key and IV are cleared by a reset.
13.9.3 Padding of input data
AES works on blocks of 128 bits. If the last
block contains less than 128 bits, it must
be padded with zeros when written to the
coprocessor.
13.9.4 Interface to CPU
The CPU communicates with the
coprocessor using three SFR registers:
• ENCCS, Encryption control and status
register
• ENCDI, Encryption input register
• ENCDO, Encryption output register
Read/write to the status register is done by
the CPU, while read/write the input/output
register is intended for use together with
direct memory access (DMA).
Two DMA channels must be used, one for
input data and one for output data. The
DMA channels must be initialized before a
start command is written to the ENCCS.
Writing a start command generates a DMA
trigger and the transfer is started. After
each block is processed, an interrupt is
generated. The interrupt is used to issue a
new start command to the ENCCS.
13.9.5 Modes of operation
ECB and CBC modes are performed as
described in section 13.9.1
When using CFB, OFB and CTR mode,
the 128 bits blocks are divided into four 32
bits blocks. 32 bits are loaded into the
AES coprocessor and the resulting 32 bits
are read out. This continues until all 128
bits are encrypted. The only time one has
to consider this is if data is loaded/read
directly using the CPU. When using DMA,
this is handled automatically by the DMA
triggers generated by the AES
coprocessor.
Both encryption and decryption are
performed similarly.
The CBC-MAC mode is a variant of the
CBC mode. When performing CBC-MAC,
data is downloaded to the coprocessor as
one block at a time, except for the last
block. Before the last block is loaded, the
mode must be changed to CBC. The last
block is then downloaded and the block
uploaded will be the MAC value.
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 135 of
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