CC2510FX Datasheet, PDF (173/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
USBCSOL.OVERRUN is set and the packet
data will be lost. Firmware can reduce the
chance for this to happen by using double
buffering and use DMA to effectively
unload data packets.
An isochronous data packet in the OUT
FIFO may have bit errors. The hardware
will detect this condition and set
USBCSOL.DATA_ERROR. Firmware should
therefore always check this bit when
unloading a data packet.
The AutoClear feature will typically not be
used for isochronous endpoints since the
packet size will increase or decrease from
frame to frame to match the source data
rate.
Notice that an isochronous endpoint
cannot be stalled.
13.15.7 DMA
DMA should be used to fill the IN endpoint
FIFOs and empty the OUT endpoint
FIFOs. Using DMA will improve read/write
performance significantly compared to
using the 8051 CPU. It is therefore highly
recommended to use DMA unless timing
is not critical or only a few bytes are to be
transferred.
There are no DMA triggers for the USB
Controller. Thus, DMA transfers must be
MSB LSB
triggered by firmware. The DMA Transfer
Mode should be set to block transfer.
The word size can be byte (8 bits) or word
(16 bits). When word size transfer is used
the ENDIAN register must be set correctly.
The ENDIAN.USBRLE bit selects whether
word data is read as little or big endian
from OUT FIFOs and the
ENDIAN.USBWLE bit selects whether word
data is written as little or big endian to IN
FIFOs. Writing and reading words for the
different settings is shown in Figure 37
and Figure 38 respectively. Notice that the
setting for these bits will be used for all
endpoints. Consequently, it is not possible
to have multiple DMA channels active at
once that use different endianness. The
ENDIAN register must be configured to
use big endian for both read and write for
a word size transfer to produce the same
result as a byte size transfer of an even
number of bytes. Refer to section 12.12 for
more information about the ENDIAN
register. Word size transfer is slightly more
efficient than byte transfer.
Refer to section 13.2 for more information
about how to use DMA.
To Host
SYNC
PID MSB LSB MSB LSB
MSB LSB
MSB LSB CRC16 EOP
To Host
SYNC
PID LSB MSB LSB MSB
LSB MSB CRC16 EOP
Figure 37 Writing Little/Big Endian
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 173 of
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