CC2510FX Datasheet, PDF (119/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
corresponding interrupt flag must be cleared
by the CPU before a new interrupt request can
be generated. Also, enabling an interrupt mask
bit will generate a new interrupt request if the
corresponding interrupt flag is set.
When the timer is used in Free-running Mode
or Modulo Mode the interrupt flags are set as
follows:
• TIMIF.TxCH0IF
TIMIF.TxCH1IF are
compare/capture event
and
set on
• TIMIF.TxOVFIF is set when counter
reaches terminal count value
When the timer is used in Up/Down Mode the
interrupt flags are set as follows:
In compare mode:
• TIMIF.TxCH0IF
and
TIMIF.TxOVFIF are set when the
counter turns around on zero
• TIMIF.TxCH1IF is set on compare
event
In capture mode:
• TIMIF.TxCH0IF
and
TIMIF.TxCH1IF are set on capture
event
• TIMIF.TxOVFIF is set when the
counter turns around on zero
13.6.7 Timer 3 and Timer 4 DMA triggers
There are two DMA triggers associated with
Timer 3 and two DMA triggers associated with
Timer 4. These are DMA triggers T3_CH0,
T3_CH1, T4_CH0 and T4_CH1 which are
generated when the corresponding interrupt
flags are set:
• T3_CH0 is generated
TIMIF.T3CH0IF is set
when
• T3_CH1 is generated
TIMIF.T3CH1IF is set
when
• T4_CH0 is generated
TIMIF.T4CH0IF is set
when
• T4_CH1 is generated
TIMIF.T4CH1IF is set
when
Refer to section 13.2 on page 84, for a
description on use of DMA channels.
13.6.8 Timer 3 and 4 registers
The Timer 3 and 4 registers are described on
the following pages.
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 119 of 252