CC2510FX Datasheet, PDF (158/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
13.14 I2S
The CC2510Fx/CC2511Fx provides an
industry standard I2S interface. The I2S
interface can be used to transfer digital
audio samples between the
CC2510Fx/CC2511Fx and an external audio
device, eg. audio DAC, audio DSP.
The I2S interface can be configured to
operate as master or slave and may use
mono as well as stereo samples. When
mono mode is enabled, the same audio
sample will be used for both channels.
Both full and half duplex is supported and
automatic µ-Law compression and
expansion can be used.
The I2S interface consists of 4 signals:
• Continous Serial Clock (SCK)
• Word Select (WS)
• Serial Data In (RX)
• Serial Data Out (TX)
When the module is in master mode, it
drives the SCK and WS lines. When the
I2S interface is in slave mode, these lines
are driven by an external master. The data
on the serial data lines is transferred most
significant bit first with one bit per SCK
cycle. The WS signal selects the channel
of the currently transferred word (left = 0,
right = 1). It also determines the length of
each word. There is a transition on the WS
line one bit time before the first word is
transferred and before the last bit of each
word. Figure 34 shows the I2S signaling.
Only a single serial data signal is shown in
this figure. The SD signal could be the RX
or TX signal depending on the direction of
the data.
The sample in the data buffer is inverted
before being sent onto the bus. Likewise,
the bits received are inverted before they
are loaded into the data buffer.
SCK
WS
SD
SAMPLE n-1,
RIGHT CHANNEL
MSB
SAMPLE n,
LEFT CHANNEL
LSB
MSB
SAMPLE n+1,
RIGHT CHANNEL
Figure 34 I2S Digital Audio Signaling
LSB
MSB
13.14.1 Enabling I2S
The I2SCFG0.ENAB bit must be set to
enable the I2S transmitter/receiver.
However, when I2SCFG0.ENAB is not set,
the I2S can still be used as a stand-alone
µ-Law compression/expansion engine.
Refer to section 13.14.12 on page 162 for
more details about this.
13.14.2 I2S Interrupts
The I2S has two RX and TX interrupts:
• I2S RX complete interrupt (I2SRX)
• I2S TX complete interrupt (I2STX)
The I2S interrupt enable bits are found in
the I2SCFG0 register. The interrupt flags
are located in the I2SSTAT register. The
interrupt enables and flags are
summarized below.
Interrupt enables:
• I2S RX: I2SCFG0.RXIEN
• I2S TX: I2SCFG0.TXIEN
Interrupt flags:
• I2S RX: I2SSTAT.RXIRQ
• I2S TX: I2SSTAT.TXIRQ
A TX interrupt is generated when the
internal TX buffer is empty and the I2S
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 158 of
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