CC2510FX Datasheet, PDF (162/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
13.14.12
µ-Law compression and
expansion
The I2S interface can be configured to
perform µ-Law compression and
expansion. µ-Law compression is enabled
by setting the I2SCFG0.ULAWC bit to 1
and µ-Law expansion is enabled by setting
the I2SCFG0.ULAWE bit to 1.
When the I2S interface is enabled, i.e. the
I2SCFG0.ENAB bit is 1, and µ-Law
expansion is enabled, every byte of µ-Law
compressed data written to the I2SDATH
register is expanded to a 16-bit sample
before being transmitted. When the I2S
interface is enabled and µ-Law
compression is enabled each sample
received is compressed to an 8-bit µ-Law
sample and put in the I2SDATH register.
When the I2S interface is disabled, i.e. the
I2SCFG0.ENAB bit is 0, it can still be used
to perform µ-Law compression/expansion
for other resources in the system. To
perform
an
expansion,
the
I2SCFG0.ULAWE must be set and the
I2SCFG0.ULAWC bit must be
cleared. Then write a byte of
compressed data to the I2SDATH
register. The expansion takes one clock
cycle to perform, and then the result can
be read from the I2SDATH:I2SDATL
registers.
To perform a compression the
I2SCFG0.ULAWC bit must be set
and the I2SCFG0.ULAWE bit must
be cleared. To start the
compression,
write
a
uncompressed 16-bit sample to
the I2SDATH:I2SDATL registers. The
compression takes one clock cycle to
perform, and then the result can be read
from the I2SDATH register.
Only one of the flags I2SCFG0.ULAWC
and I2SCFG0.ULAWE should be set when
the I2S interface is used without the
I2SCFG0.ENAB bit is set.
13.14.13
I2S Registers
This section describes all I2S registers
used for control and status for the I2S. The
USB registers reside in XDATA memory
space in the region 0xDF40-0xDF48.
Table 49 gives an overview of register
addresses while the remaining tables in
this section describe each register. Notice
that the reset values for the registers
reflect a configuration with 16-bit stereo
samples and 44.1 kHz sample rate. The
I2S is not enabled at reset.
XDATA
Address Register Description
0xDF40
0xDF41
0xDF42
0xDF43
0xDF44
0xDF45
0xDF46
0xDF47
0xDF48
I2SCFG0
I2SCFG1
I2SDATL
I2SDATH
I2SWCNT
I2SSTAT
I2SCLKF0
I2SCLKF1
I2SCLKF2
I2S Configuration Register 0
I2S Configuration Register 1
I2S Data Low Byte
I2S Data High Byte
I2S Word Count Register
I2S Status Register
I2S Clock Configuration Register 0
I2S Clock Configuration Register 1
I2S Clock Configuration Register 2
Table 49 Overview of I2S Registers
Bit Field Name
7 _TXIEN
0xDF40: I2SCFG0 – I2S Configuration Register 0
Reset
R/W Description
0
R/W Transmit interrupt enable.
0 interrupts are disabled
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 162 of
252