CC2510FX Datasheet, PDF (129/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
13.7.2.5 ADC Conversion Results
The digital conversion result is
represented in two's complement form.
For 14-bit resolution, the digital conversion
result is 8191 when the analogue input is
equal to the VREF, and the conversion
result is -8192 when the analogue input is
equal to –VREF, where VREF is the
selected positive voltage reference.
When single-ended input is used, only
positive conversion results are generated
effectively reducing the resolution to
maximum 13 bits.
The digital conversion result is available
when ADCCON1.EOC is set to 1, in ADCH
and ADCL.
When reading the ADCCON2.SCH field,
the number returned will indicate the last
channel converted. Notice that when the
value written to ADCCON2.SCH is less
than 12, the number returned will be the
number of the last channel converted + 1.
13.7.2.6 ADC Reference Voltage
The positive reference voltage for
analogue-to-digital conversions is
selectable as either an internally
generated 1.25V voltage, the AVDD pin,
the external voltage applied to the AIN7
input pin or the differential voltage applied
to the AIN6-AIN7 inputs.
It is possible to select the reference
voltage as the input to the ADC in order to
perform a conversion of the reference
voltage e.g. for calibration purposes.
Similarly, it is possible to select the ground
terminal GND as an input.
13.7.2.7 ADC Conversion Timing
The 26/48 MHz crystal oscillator should be
selected when the ADC is used. The ADC
runs on a clock which is the 26/48 MHz
system clock source divided by 6 to give a
4.33/4 MHz ADC clock. The delta sigma
modulator and decimation filter both use
the ADC clock for their calculations.
The time required to perform a conversion
depends on the selected decimation rate.
When the decimation rate is set to for
instance 128, the decimation filter uses
exactly 128 of the ADC clock periods to
calculate the result. When a conversion is
started, the input multiplexer is allowed 16
ADC clock cycles to settle in case the
channel has been changed since the
previous conversion. The 16 clock cycles
settling time applies to all decimation
rates. Thus in general, the conversion time
is given by:
Tconv = (decimation rate + 16) x T
where
T = 0.23 µs for CC2510Fx
T = 0.25 µs for CC2511Fx
13.7.2.8 ADC Interrupts
The ADC will generate an interrupt when
an extra conversion has completed. An
interrupt is not generated when a
conversion from the sequence is
completed.
13.7.2.9 ADC DMA Triggers
The ADC will generate a DMA trigger
every time a conversion from the
sequence has completed. When an extra
conversion completes, no DMA trigger is
generated.
There is one DMA trigger for each of the
eight channels defined by the first eight
possible settings for ADCCON2.SCH . The
DMA trigger is active when a new sample
is ready from the conversion for the
channel. The DMA triggers are named
ADC_CHx in Table 42 on page 90.
In addition there is one DMA trigger,
ADC_CHALL, which is active when new
data is ready from any of the channels in
the ADC conversion sequence.
13.7.2.10 ADC Registers
This section describes the ADC registers.
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 129 of
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