CC2510FX Datasheet, PDF (159/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
fetches the new data previously written to
the I2SDATH:I2SDATL registers. The TX
interrupt flag, I2SSTAT.TXIRQ, is cleared
when I2SDATH register is written.
An RX interrupt is generated when the
internal RX buffer is full and the contents
of the RX buffer is copied to the pair of
internal data registers that can be read
from the I2SDATH:I2SDATL registers.
The RX interrupt flag, I2SSTAT.TXIRQ,
is cleared when the I2SDATH register is
read.
Notice that interrupts will also be
generated if the corresponding RXIRQ or
TXIRQ flags are set from software.
The I2S shares interrupt vector with
USART 1. Refer to section 12.7 on page
49 for more details about interrupts.
13.14.3 I2S DMA Triggers
There are two DMA triggers associated
with the I2S interface. The DMA triggers
are activated by RX complete and TX
complete events, i.e. the same events as
the I2S interrupt requests. The DMA
triggers are not masked by the interrupt
enable bits, I2SCFG0.RXIEN and
I2SCFG0.TXIEN. A DMA channel thus
can be configured using the I2S
receive/transmit
data
registers,
I2SDATH:I2SDATL, as source or
destination address and use the I2S DMA
triggers.
Notice that I2SRX / ADC_CH6 and I2STX
/ ADC_CH7 DMA trigger pairs use the
same DMA trigger numbers. Thus, only
one of I2SRX and ADC_CH6 and one of
I2STX and ADC_CH7 can be used
simultaneously. On the CC2511Fx ADC
channels 7 and 8 cannot be used since
P0_6 and P0_7 I/O pins are not available.
Refer to Table 42 on page 90 for an
overview of the DMA triggers.
13.14.4 Underflow/Overflow
If the I2S attempts to read from the
internal TX buffer when it is empty, an
underflow condition occurs. The I2S will
then continue to read from the data in the
TX buffer, and the TXUNF flag of the
I2SSTAT register will be set.
If the I2S attempts to write to the internal
RX buffer while it is full, an overflow
condition occurs. The contents of the RX
buffer will be overwritten and the RXOVF
flag of the I2SSTAT register will be set.
Thus, when debugging an application,
software may check for underflow/overflow
when an interrupt is generated or when
the application completes. The
TXUNF/RXOVF flags should be cleared in
software.
13.14.5 Writing a word (TX)
When each sample fits into a single byte
or µ-Law compressed samples (always 8
bits) are written, i.e. µ-Law expansion is
enabled, only the I2SDATH register needs
to be written.
When each sample is more than 8 bits the
low byte must be written to the I2SDATL
register before the high byte is written to
the I2SDATH register.
Thus, writing the I2SDATH register
signifies the completion of the write
operation.
When the I2S is configured to send stereo,
i.e. I2SCFG0.TXMONO is 0, the
I2SSTAT.TXLR flag can be used to
determine whether the left- or right-
channel sample is to be written to the data
registers.
13.14.6 Reading a word (RX)
If each sample fits into a single byte or µ-
Law compression is enabled, only the
I2SDATH register needs to be read.
When each sample is more than 8 bits the
low byte must be read from the I2SDATL
register before the high byte is being read
from the I2SDATH register.
Thus, reading from the I2SDATH register
signifies the completion of the read
operation.
When the I2S is configured to receive
stereo, i.e. I2SCFG0.RXMONO is 0, the
I2SSTAT.RXLR flag can be used to
determine whether the sample currently in
the data registers is a left- or right-channel
sample.
13.14.7 Full vs. half duplex
The I2S interface supports full duplex and
half duplex operation.
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 159 of
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