LM3S8730 Datasheet, PDF (9/502 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8730 Microcontroller
Figure 15-1. CAN Module Block Diagram ........................................................................................... 367
Figure 15-2. CAN Bit Time ................................................................................................................ 374
Figure 16-1. Ethernet Controller Block Diagram .................................................................................. 408
Figure 16-2. Ethernet Controller ......................................................................................................... 408
Figure 16-3. Ethernet Frame ............................................................................................................. 410
Figure 17-1. Pin Connection Diagram ................................................................................................ 452
Figure 20-1. Load Conditions ............................................................................................................ 468
Figure 20-2. I²C Timing ..................................................................................................................... 470
Figure 20-3. External XTLP Oscillator Characteristics ......................................................................... 472
Figure 20-4. Hibernation Module Timing ............................................................................................. 473
Figure 20-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 474
Figure 20-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 474
Figure 20-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 475
Figure 20-8. JTAG Test Clock Input Timing ......................................................................................... 476
Figure 20-9. JTAG Test Access Port (TAP) Timing .............................................................................. 476
Figure 20-10. JTAG TRST Timing ........................................................................................................ 476
Figure 20-11. External Reset Timing (RST) .......................................................................................... 477
Figure 20-12. Power-On Reset Timing ................................................................................................. 478
Figure 20-13. Brown-Out Reset Timing ................................................................................................ 478
Figure 20-14. Software Reset Timing ................................................................................................... 478
Figure 20-15. Watchdog Reset Timing ................................................................................................. 478
Figure 21-1. 100-Pin LQFP Package .................................................................................................. 479
September 02, 2007
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Preliminary