LM3S8730 Datasheet, PDF (77/502 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8730 Microcontroller
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
DSDIVORIDE
reserved
Type RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DSOSCSRC
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:29
28:23
22:7
6:4
Name
reserved
DSDIVORIDE
reserved
DSOSCSRC
Type
RO
R/W
RO
R/W
Reset
0x0
0x0F
0x0
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Divider Field Override
6-bit system divider field to override when Deep-Sleep occurs with PLL
running.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clock Source
When set, forces IOSC to be clock source during Deep Sleep mode.
Value Name Description
0x0 NOORIDE No override to the oscillator clock source is done
0x1 IOSC
Use internal 12 MHz oscillator as source
0x3 30kHz Use 30 kHz internal oscillator
0x7 32kHz Use 32 kHz external oscillator
3:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
September 02, 2007
77
Preliminary