LM3S8730 Datasheet, PDF (14/502 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 193
General-Purpose Timers ............................................................................................................. 194
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 206
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 207
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 209
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 211
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 214
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 216
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 217
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 218
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 220
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 221
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 222
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 223
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 224
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 225
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 226
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 227
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 228
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 229
Watchdog Timer ........................................................................................................................... 230
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 233
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 234
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 235
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 236
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 237
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 238
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 239
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 240
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 241
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 242
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 243
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 244
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 245
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 246
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 247
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 248
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 249
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 250
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 251
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 252
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 253
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 261
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 263
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 265
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 267
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 268
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 269
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September 02, 2007
Preliminary