LM3S8730 Datasheet, PDF (414/502 Pages) List of Unclassifed Manufacturers – Microcontroller

Ethernet Controller
7. To receive a frame, wait for the NPR field in the MACNP register to be non-zero. Then begin
reading the frame from the RX FIFO by using the MACDATA register. When the frame (including
the FCS field) has been read, the NPR field should decrement by one. When there are no more
frames in the RX FIFO, the NPR field will read 0.
16.4
Ethernet Register Map
Table 16-2 on page 414 lists the Ethernet MAC registers. All addresses given are relative to the
Ethernet MAC base address of 0x4004.8000.
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY.
The registers are collectively known as the MII Management registers and are detailed in Section
22.2.4 of the IEEE 802.3 specification. Table 16-2 on page 414 also lists these MII Management
registers. All addresses given are absolute and are written directly to the REGADR field of the
MACMCTL register. The format of registers 0 to 15 are defined by the IEEE specification and are
common to all PHY implementations. The only variance allowed is for features that may or may not
be supported by a specific PHY. Registers 16 to 31 are vendor-specific registers, used to support
features that are specific to a vendors PHY implementation. Vendor-specific registers not listed are
reserved.
Table 16-2. Ethernet Register Map
Offset Name
Type
Ethernet MAC
0x000 MACRIS
0x000 MACIACK
0x004 MACIM
0x008 MACRCTL
0x00C MACTCTL
0x010 MACDATA
0x014 MACIA0
0x018 MACIA1
0x01C MACTHR
0x020 MACMCTL
0x024 MACMDV
0x02C MACMTXD
0x030 MACMRXD
0x034 MACNP
0x038 MACTR
0x03C MACTS
MII Management
-
MR0
RO
W1C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
Reset
Description
0x0000.0000
0x0000.0000
0x0000.007F
0x0000.0008
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.003F
0x0000.0000
0x0000.0080
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
Ethernet MAC Raw Interrupt Status
Ethernet MAC Interrupt Acknowledge
Ethernet MAC Interrupt Mask
Ethernet MAC Receive Control
Ethernet MAC Transmit Control
Ethernet MAC Data
Ethernet MAC Individual Address 0
Ethernet MAC Individual Address 1
Ethernet MAC Threshold
Ethernet MAC Management Control
Ethernet MAC Management Divider
Ethernet MAC Management Transmit Data
Ethernet MAC Management Receive Data
Ethernet MAC Number of Packets
Ethernet MAC Transmission Request
Ethernet MAC Timer Support
0x3100
Ethernet PHY Management Register 0 – Control
See
page
416
418
419
420
421
422
424
425
426
427
428
429
430
431
432
433
434
414
September 02, 2007
Preliminary