LM3S8730 Datasheet, PDF (314/502 Pages) List of Unclassifed Manufacturers – Microcontroller

Synchronous Serial Interface (SSI)
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding
mask.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TXIM RXIM RTIM RORIM
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
Name
reserved
TXIM
Type
RO
R/W
Reset
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Transmit FIFO Interrupt Mask
The TXIM values are defined as follows:
Value Description
0 TX FIFO half-full or less condition interrupt is masked.
1 TX FIFO half-full or less condition interrupt is not masked.
2
RXIM
R/W
0
SSI Receive FIFO Interrupt Mask
The TFE values are defined as follows:
Value Description
0 RX FIFO half-full or more condition interrupt is masked.
1 RX FIFO half-full or more condition interrupt is not masked.
1
RTIM
R/W
0
SSI Receive Time-Out Interrupt Mask
The RTIM values are defined as follows:
Value Description
0 RX FIFO time-out interrupt is masked.
1 RX FIFO time-out interrupt is not masked.
314
September 02, 2007
Preliminary