LM3S8730 Datasheet, PDF (416/502 Pages) List of Unclassifed Manufacturers – Microcontroller

Ethernet Controller
Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000
The MACRIS register is the interrupt status register. On a read, this register gives the current status
value of the corresponding interrupt prior to masking.
Ethernet MAC Raw Interrupt Status (MACRIS)
Base 0x4004.8000
Offset 0x000
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PHYINT MDINT RXER FOV TXEMP TXER RXINT
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:7
6
5
4
Name
reserved
PHYINT
MDINT
RXER
Type
RO
RO
RO
RO
Reset
0x0
0x0
0x0
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PHY Interrupt
When set, indicates that an enabled interrupt in the PHY layer has
occured. MR17 in the PHY must be read to determine the specific PHY
event that triggered this interrupt.
MII Transaction Complete
When set, indicates that a transaction (read or write) on the MII interface
has completed successfully.
Receive Error
This bit indicates that an error was encountered on the receiver. The
possible errors that can cause this interrupt bit to be set are:
■ A receive error occurs during the reception of a frame (100 Mb/s
only).
■ The frame is not an integer number of bytes (dribble bits) due to an
alignment error.
■ The CRC of the frame does not pass the FCS check.
■ The length/type field is inconsistent with the frame data size when
interpreted as a length field.
3
FOV
RO
0x0
FIFO Overrrun
When set, indicates that an overrun was encountered on the receive
FIFO.
2
TXEMP
RO
0x0
Transmit FIFO Empty
When set, indicates that the packet was transmitted and that the TX
FIFO is empty.
416
September 02, 2007
Preliminary