LM3S8730 Datasheet, PDF (222/502 Pages) List of Unclassifed Manufacturers – Microcontroller

General-Purpose Timers
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerA Match (GPTMTAMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x030
Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TAMRH
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
1
1
0
1
0
1
1
1
1
0
1
1
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TAMRL
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit/Field
31:16
15:0
Name
TAMRH
TAMRL
Type
Reset Description
R/W
0xFFFF GPTM TimerA Match Register High
(32-bit mode)
0x0000 (16-bit ^{When configured for 32-bit Real-Time Clock (RTC) mode via the}
mode) ^{GPTMCFG register, this value is compared to the upper half of}
GPTMTAR, to determine match events.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBMATCHR.
R/W
0xFFFF GPTM TimerA Match Register Low
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the lower half of
GPTMTAR, to determine match events.
When configured for PWM mode, this value along with GPTMTAILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTAILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTAILR
minus this value.
222
September 02, 2007
Preliminary