LM3S8730 Datasheet, PDF (469/502 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8730 Microcontroller
20.2.3
Parameter Parameter Name
Min
f_MOSC
Main oscillator frequency
1
t_{MOSC_per}
Main oscillator period
125
f_{ref_crystal_bypass} Crystal reference using the main oscillator (PLL in BYPASS mode) 1
f_{ref_ext_bypass} External clock reference (PLL in BYPASS mode)
0
f_{system_clock}
System clock
0
Nom
-
-
-
-
-
Max Unit
8 MHz
1000 ns
8 MHz
50 MHz
50 MHz
Table 20-7. Crystal Characteristics
Parameter Name
Value
Units
Frequency
8
6
4
3.5 MHz
Frequency tolerance
±50 ±50 ±50 ±50 ppm
Aging
±5
±5
±5
±5 ppm/yr
Oscillation mode
Parallel Parallel Parallel Parallel
Temperature stability (0 - 85 °C) ±25 ±25 ±25 ±25 ppm
Motional capacitance (typ)
27.8 37.0 55.6 63.5 pF
Motional inductance (typ)
14.3 19.1 28.6 32.7 mH
Equivalent series resistance (max) 120 160 200 220 Ω
Shunt capacitance (max)
10
10
10
10
pF
Load capacitance (typ)
16
16
16
16
pF
Drive level (typ)
100 100 100 100 µW
I²C
Table 20-8. I²C Characteristics
Parameter No. Parameter Parameter Name
Min Nom Max
Unit
I1^a
t_SCH Start condition hold time
36 -
-
system clocks
I2^a
t_LP
Clock Low period
36 -
-
system clocks
I3^b
t_SRT I2CSCL/I2CSDA rise time (V_IL =0.5 V to V _IH =2.4 V) - - (see note b)
ns
I4^a
t_DH Data hold time
2-
-
system clocks
I5^c
t_SFT I2CSCL/I2CSDA fall time (V_IH =2.4 V to V _IL =0.5 V) - 9
10
ns
I6^a
t_HT Clock High time
24 -
-
system clocks
I7^a
t_DS Data setup time
18 -
-
system clocks
I8^a
t_SCSR Start condition setup time (for repeated start condition 36 -
-
system clocks
only)
I9^a
t_SCS Stop condition setup time
24 -
-
system clocks
a. Values depend on the value programmed into the TPR bit in the I²C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I ²C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
September 02, 2007
469
Preliminary