LM3S601 Datasheet, PDF (74/446 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Bit/Field
19:17
16:14
13
12
11
10
Name
PWMDIV
reserved
PWRDN
OEN
BYPASS
PLLVER
Type
R/W
RO
R/W
R/W
R/W
R/W
Reset
0x7
Description
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the system clock
down for use as the timing reference for the PWM module. This clock
is only power 2 divide and rising edge is synchronous without phase
shift from the system clock.
Value Divisor
0x0 /2
0x1 /4
0x2 /8
0x3 /16
0x4 /32
0x5 /64
0x6 /64
0x7 /64 (default)
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL. See Table 6-2 on page 76 for PLL mode control.
1
PLL Output Enable
This bit specifies whether the PLL output driver is enabled. If cleared,
the driver transmits the PLL clock to the output. Otherwise, the PLL
clock does not oscillate outside the PLL module.
Note: Both PWRDN and OEN must be cleared to run the PLL.
1
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
0
PLL Verification
This bit controls the PLL verification timer function. If set, the verification
timer is enabled and an interrupt is generated if the PLL becomes
inoperative. Otherwise, the verification timer is not enabled.
74
October 01, 2007
Preliminary