LM3S601 Datasheet, PDF (73/446 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S601 Microcontroller
Bit/Field
26:23
22
21
20
Name
SYSDIV
USESYSDIV
reserved
USEPWMDIV
Type
R/W
R/W
RO
R/W
Reset
0xF
0
0
0
Description
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 200 MHz.
Value Divisor (BYPASS=1) Frequency (BYPASS=0)
0x0 reserved
reserved
0x1 /2
reserved
0x2 /3
reserved
0x3 /4
50 MHz
0x4 /5
40 MHz
0x5 /6
33.33 MHz
0x6 /7
28.57 MHz
0x7 /8
25 MHz
0x8 /9
22.22 MHz
0x9 /10
20 MHz
0xA /11
18.18 MHz
0xB /12
16.67 MHz
0xC /13
15.38 MHz
0xD /14
14.29 MHz
0xE /15
13.33 MHz
0xF /16
12.5 MHz (default)
When reading the Run-Mode Clock Configuration (RCC) register (see
page 72), the SYSDIV value is MINSYSDIV if a lower divider was
requested and the PLL is being used. This lower value is allowed to
divide a non-PLL source.
Enable System Clock Divider
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Enable PWM Clock Divisor
Use the PWM clock divider as the source for the PWM clock.
October 01, 2007
73
Preliminary