LM3S601 Datasheet, PDF (12/446 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
List of Registers
System Control .............................................................................................................................. 54
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 63
Register 2: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 .................................... 65
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 66
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 67
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 68
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 70
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 71
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 72
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 77
Register 10: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 78
Register 11: Clock Verification Clear (CLKVCLR), offset 0x150 ............................................................. 79
Register 12: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 ................................... 80
Register 13: Device Identification 1 (DID1), offset 0x004 ....................................................................... 81
Register 14: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 83
Register 15: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 84
Register 16: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 86
Register 17: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 88
Register 18: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 90
Register 19: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 91
Register 20: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 92
Register 21: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 93
Register 22: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 94
Register 23: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 97
Register 24: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 100
Register 25: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 103
Register 26: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 105
Register 27: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 107
Register 28: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 109
Register 29: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 110
Register 30: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 112
Internal Memory ........................................................................................................................... 113
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 119
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 120
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 121
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 123
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 124
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 125
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 126
Register 8: Flash Memory Protection Read Enable (FMPRE), offset 0x130 ......................................... 127
Register 9: Flash Memory Protection Program Enable (FMPPE), offset 0x134 .................................... 128
General-Purpose Input/Outputs (GPIOs) ................................................................................... 129
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 137
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 138
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 139
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October 01, 2007
Preliminary