LM3S601 Datasheet, PDF (404/446 Pages) List of Unclassifed Manufacturers – Microcontroller

Signal Tables
18
Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register.
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.
Table 18-1 on page 404 shows the pin-to-signal-name mapping, including functional characteristics
of the signals. Table 18-2 on page 406 lists the signals in alphabetical order by signal name.
Table 18-3 on page 409 groups the signals by functionality, except for GPIOs. Table 18-4 on page
410 lists the GPIO pins and their alternate functionality.
Table 18-1. Signals by Pin Number
Pin Number
1
2
3
4
5
6
Pin Name
PE5
CCP5
PE4
CCP3
PE3
CCP1
PE2
CCP4
RST
LDO
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
-
7
VDD
-
8
GND
-
9
OSC0
I
10
OSC1
O
11
PC7
I/O
C2-
I
12
PC6
I/O
C2+
I
PhB
I
13
PC5
I/O
C1+
I
C0o
O
14
PC4
I/O
PhA
I
15
VDD
-
16
GND
-
17
PA0
I/O
U0Rx
I
Buffer Type Description
TTL
GPIO port E bit 5
TTL
Capture/Compare/PWM 5
TTL
GPIO port E bit 4
TTL
Capture/Compare/PWM 3
TTL
GPIO port E bit 3
TTL
Capture/Compare/PWM 1
TTL
GPIO port E bit 2
TTL
Capture/Compare/PWM 4
TTL
System reset input.
Power
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 µF or greater.
Power Positive supply for I/O and some logic.
Power Ground reference for logic and I/O pins.
Analog
Main oscillator crystal input or an external
clock reference input.
Analog Main oscillator crystal output.
TTL
GPIO port C bit 7
Analog Analog comparator 2 negative input
TTL
GPIO port C bit 6
Analog Analog comparator positive input
TTL
QEI module 0 Phase B
TTL
GPIO port C bit 5
Analog Analog comparator positive input
TTL
Analog comparator 0 output
TTL
GPIO port C bit 4
TTL
QEI module 0 Phase A
Power Positive supply for I/O and some logic.
Power Ground reference for logic and I/O pins.
TTL
GPIO port A bit 0
TTL
UART module 0 receive
404
October 01, 2007
Preliminary