LM3S601 Datasheet, PDF (55/446 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S601 Microcontroller
6.1.2.3
1. The external reset pin (RST) is asserted and then de-asserted.
2. After RST is de-asserted, the main crystal oscillator is allowed to settle and there is an internal
main oscillator counter that takes from 15-30 ms to account for this. During this time, internal
reset to the rest of the controller is held active.
3. The internal reset is released and the core fetches and loads the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
The external reset timing is shown in Figure 20-9 on page 421.
Power-On Reset (POR)
The Power-On Reset (POR) circuitry detects a rise in power-supply voltage (V_DD) and generates
an on-chip reset pulse. To use the on-chip circuitry, the RST input needs to be connected to the
power supply (V_DD) through a pull-up resistor (1K to 10K Ω).
The device must be operating within the specified operating parameters at the point when the on-chip
power-on reset pulse is complete. The specified operating parameters include supply voltage,
frequency, temperature, and so on. If the operating conditions are not met at the point of POR end,
the Stellaris^® controller does not operate correctly. In this case, the reset must be extended using
external circuitry. The RST input may be used with the circuit as shown in Figure 6-1 on page 55.
Figure 6-1. External Circuitry to Extend Reset
D₁
R₁
R₂
C₁
Stellaris
RST
6.1.2.4
The R₁ and C₁ components define the power-on delay. The R₂ resistor mitigates any leakage from
the RST input. The diode (D₁) discharges C₁ rapidly when the power supply is turned off.
The Power-On Reset sequence is as follows:
1. The controller waits for the later of external reset (RST) or internal POR to go inactive.
2. After the resets are inactive, the main crystal oscillator is allowed to settle and there is an internal
main oscillator counter that takes from 15-30 ms to account for this. During this time, internal
reset to the rest of the controller is held active.
3. The internal reset is released and the core fetches and loads the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing
is shown in Figure 20-10 on page 421.
Note: The power-on reset also resets the JTAG controller. An external reset does not.
Brown-Out Reset (BOR)
A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used
to reset the controller. This is initially disabled and may be enabled by software.
October 01, 2007
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Preliminary