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LM3S601 Datasheet, PDF (232/446 Pages) List of Unclassifed Manufacturers – Microcontroller
Universal Asynchronous Receivers/Transmitters (UARTs)
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 240) should be set to 10.
The value to be loaded into the UARTFBRD register (see page 241) is calculated by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Enable the UART by setting the UARTEN bit in the UARTCTL register.
11.4
Register Map
Table 11-1 on page 232 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:
■ UART0: 0x4000.C000
■ UART1: 0x4000.D000
Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 244)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 11-1. UART Register Map
Offset Name
Type
0x000 UARTDR
R/W
0x004 UARTRSR/UARTECR R/W
0x018 UARTFR
RO
0x024 UARTIBRD
R/W
0x028 UARTFBRD
R/W
0x02C UARTLCRH
R/W
0x030 UARTCTL
R/W
0x034 UARTIFLS
R/W
0x038 UARTIM
R/W
0x03C UARTRIS
RO
0x040 UARTMIS
RO
Reset
0x0000.0000
0x0000.0000
0x0000.0090
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0300
0x0000.0012
0x0000.0000
0x0000.000F
0x0000.0000
Description
UART Data
UART Receive Status/Error Clear
UART Flag
UART Integer Baud-Rate Divisor
UART Fractional Baud-Rate Divisor
UART Line Control
UART Control
UART Interrupt FIFO Level Select
UART Interrupt Mask
UART Raw Interrupt Status
UART Masked Interrupt Status
See
page
234
236
238
240
241
242
244
245
247
249
250
232
October 01, 2007
Preliminary