LM3S601 Datasheet, PDF (65/446 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S601 Microcontroller
Register 2: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Power-On and Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFD
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BORTIM
BORIOR BORWT
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Bit/Field
31:16
15:2
1
0
Name
reserved
BORTIM
BORIOR
BORWT
Type
RO
R/W
R/W
R/W
Reset Description
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x1FFF
BOR Time Delay
This field specifies the number of internal oscillator clocks delayed before
the BOR output is resampled if the BORWT bit is set.
The width of this field is derived by the t _BOR width of 500 μs and the
internal oscillator (IOSC) frequency of 12 MHz ± 30%. At +30%, the
counter value has to exceed 7,800.
0
BOR Interrupt or Reset
This bit controls how a BOR event is signaled to the controller. If set, a
reset is signaled. Otherwise, an interrupt is signaled.
1
BOR Wait and Check for Noise
This bit specifies the response to a brown-out signal assertion if BORIOR
is not set.
If BORWT is set to 1 and BORIOR is cleared to 0, the controller waits
BORTIM IOSC periods and resamples the BOR output. If still asserted,
a BOR interrupt is signalled. If no longer asserted, the initial assertion
is suppressed (attributable to noise).
If BORWT is 0, BOR assertions do not resample the output and any
condition is reported immediately if enabled.
October 01, 2007
65
Preliminary