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LM3S601 Datasheet, PDF (22/446 Pages) List of Unclassifed Manufacturers – Microcontroller | |||
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Architectural Overview
â Reset generation logic with an enable/disable
â User-enabled stalling when the controller asserts the CPU Halt flag during debug
â Synchronous Serial Interface (SSI)
â Master or slave operation
â Programmable clock bit rate and prescale
â Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
â Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
â Programmable data frame size from 4 to 16 bits
â Internal loopback test mode for diagnostic/debug testing
â UART
â Two fully programmable 16C550-type UARTs
â Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
â Programmable baud-rate generator with fractional divider
â Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
â FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
â Standard asynchronous communication bits for start, stop, and parity
â False-start-bit detection
â Line-break generation and detection
â Analog Comparators
â Three independent integrated analog comparators
â Configurable for output to: drive an output pin or generate an interrupt
â Compare external pin input to external pin input or to internal programmable voltage reference
â I2C
â Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
â Interrupt generation
â Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
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October 01, 2007
Preliminary
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