LM3S601 Datasheet, PDF (302/446 Pages) List of Unclassifed Manufacturers – Microcontroller

Inter-Integrated Circuit (I²C) Interface
13
13.1
Inter-Integrated Circuit (I²C) Interface
The Inter-Integrated Circuit (I²C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I²C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I²C
bus may also be used for system testing and diagnostic purposes in product development and
manufacture. The LM3S601 microcontroller includes one I²C module, providing the ability to interact
(both send and receive) with other I²C devices on the bus.
Devices on the I²C bus can be designated as either a master or a slave. The Stellaris^® I²C module
supports both sending and receiving data as either a master or a slave, and also supports the
simultaneous operation as both a master and a slave. There are a total of four I²C modes: Master
Transmit, Master Receive, Slave Transmit, and Slave Receive. The Stellaris^® I²C module can
operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
Both the I²C master and slave can generate interrupts; the I²C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error) and the I²C slave generates
interrupts when data has been sent or requested by a master.
Block Diagram
Figure 13-1. I²C Block Diagram
13.2
Interrupt
I²C Control
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMMIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIM
I2CSRIS
I2CSMIS
I2CSICR
I²C Master Core
I2CSCL
I2CSDA
I²C Slave Core
I2CSCL
I2CSDA
I²C I/O Select
I2CSCL
I2CSDA
Functional Description
I²C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I²C bus configuration is shown in Figure 13-2 on page 303.
See “I²C” on page 416 for I²C timing diagrams.
302
October 01, 2007
Preliminary