LM3S601 Datasheet, PDF (40/446 Pages) List of Unclassifed Manufacturers – Microcontroller

Memory Map
3 Memory Map
The memory map for the LM3S601 controller is provided in Table 3-1 on page 40.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Important: In Table 3-1 on page 40, addresses not listed are reserved.
Table 3-1. Memory Map^a
Start
End
Memory
0x0000.0000
0x2000.0000
0x2010.0000
0x2200.0000
0x2204.0000
FiRM Peripherals
0x4000.0000
0x4000.4000
0x4000.5000
0x4000.6000
0x4000.7000
0x4000.8000
0x4000.C000
0x4000.D000
Peripherals
0x4002.0000
0x4002.0800
0x4002.4000
0x4002.8000
0x4002.C000
0x4003.0000
0x4003.1000
0x4003.2000
0x4003.C000
0x400F.D000
0x400F.E000
0x4200.0000
Private Peripheral Bus
0x0000.7FFF
0x2000.1FFF
0x200F.FFFF
0x22003.FFFF
0x23FF.FFFF
0x4000.0FFF
0x4000.4FFF
0x4000.5FFF
0x4000.6FFF
0x4000.7FFF
0x4000.8FFF
0x4000.CFFF
0x4000.DFFF
0x4002.07FF
0x4002.0FFF
0x4002.7FFF
0x4002.8FFF
0x4002.CFFF
0x4003.0FFF
0x4003.1FFF
0x4003.2FFF
0x4003.CFFF
0x400F.DFFF
0x400F.FFFF
0x43FF.FFFF
Description
On-chip flash ^b
Bit-banded on-chip SRAM^c
Reserved
Bit-band alias of 0x2000.0000 through 0x200F.FFFF
Reserved
For details on
registers, see
page ...
118
118
-
113
-
Watchdog timer
206
GPIO Port A
136
GPIO Port B
136
GPIO Port C
136
GPIO Port D
136
SSI0
276
UART0
233
UART1
233
I2C Master 0
315
I2C Slave 0
328
GPIO Port E
136
PWM
357
QEI0
390
Timer0
179
Timer1
179
Timer2
179
Analog Comparators
337
Flash control
118
System control
62
Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
-
40
October 01, 2007
Preliminary