LM3S601 Datasheet, PDF (14/446 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 208
Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 209
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 210
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 211
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 212
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 213
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 214
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 215
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 216
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 217
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 218
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 219
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 220
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 221
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 222
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 223
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 224
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 225
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 226
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 227
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 234
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 236
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 238
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 240
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 241
Register 6: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 242
Register 7: UART Control (UARTCTL), offset 0x030 ......................................................................... 244
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 245
Register 9: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 247
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 249
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 250
Register 12: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 251
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 253
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 254
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 255
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 256
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 257
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 258
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 259
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 260
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 261
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 262
Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 263
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 264
Synchronous Serial Interface (SSI) ............................................................................................ 265
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 277
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 279
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 281
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October 01, 2007
Preliminary