English
Language : 

M14D1G1664A-2D Datasheet, PDF (9/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle
◁
ESMT
M14D1G1664A (2D)
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
Symbol
Min.
-1.8/ 2.5/ 3
Max.
Unit Note
Input High (Logic 1) Voltage VIH(AC)
VREF + 0.2
VDDQ + VPEAK
V
Input Low (Logic 0) Voltage
VIL(AC)
VSSQ - VPEAK
VREF - 0.2
V
Input Differential Voltage
VID(AC)
0.5
VDDQ
V
1
Input Crossing Point Voltage VIX(AC) 0.5 x VDDQ - 0.175 0.5 x VDDQ + 0.175
V
2
Output Crossing Point Voltage VOX(AC) 0.5 x VDDQ - 0.125 0.5 x VDDQ + 0.125
V
3
Note:
1. VID(AC) specifies the allowable DC execution of each input of differential pair such as CLK, CLK , DQS, DQS .
2. VIX(AC) specifies the input differential voltage |VTR – VCP| required for switching, where VTR is the true input signal (such
as CLK,DQS) and VCP is the complementary input signal (such as CLK , DQS ). The minimum value is equal to VIH(DC) –
VIL(DC).
3. The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VOX(AC) is expected to
track variations in VDDQ. VOX(AC) indicates the voltage at which differential input / output signals must cross.
Input / Output Capacitance
Parameter
Input capacitance
(A0~A12, BA0~BA2, CKE, CS , RAS , CAS , WE , ODT)
-1.8/ 2.5
-3
Input capacitance (CLK, CLK )
Symbol
CIN1
CIN2
DQS, DQS & Data input/output capacitance
-1.8/ 2.5/ 3 CI / O
Input capacitance (DM)
Note: 1. Capacitance delta is 0.25 pF.
2. Capacitance delta is 0.5 pF.
-1.8/ 2.5/ 3 CIN3
Min.
1.0
1.0
1.0
2.5
2.5
Max.
1.75
2.0
2.0
3.5
3.5
Unit Note
pF 1
pF 1
pF 2
pF 2
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2013
Revision : 1.3
9/64
 ▷