M14D1G1664A-2D Datasheet, PDF (17/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D1G1664A (2D)
AC Timing Parameter & Specifications - Contiuned
Parameter
CKE minimum pulse width
(high and low pulse width)
Minimum time clocks remains
ON after CKE asynchronously
drops low
Output impedance test driver
delay
MRS command to ODT update
delay
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down
mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down
mode)
ODT to Power-Down entry
latency
ODT Power-Down exit latency
Symbol
t_CKE
-2.5
Min.
3
Max.
-
-3
Min.
3
Max.
-
t_DELAY t_IS + t_CK (avg)+t_IH
-
t_IS + t_CK (avg)+t_IH
-
t_OIT
0
12
0
12
t_MOD
0
12
0
12
t_AOND
t_AON
t_AONPD
t_AOFD
t_AOF
t_AOFPD
2
2
2
2
t_AC(min.) t_AC(max.) + 700
t_AC(min.)
t_AC(min.) + 2000
2 x t_CK
+t_AC(max.) +
1000
t_AC(min.) + 2000
t_AC(max.) +
700
2 x t_CK
+t_AC(max.) +
1000
2.5
2.5
2.5
2.5
t_AC(min.) t_AC(max.) + 600
t_AC(min.) + 2000
2.5 x t_CK
+t_AC(max.) +
1000
t_AC(min.)
t_AC(min.) + 2000
t_AC(max.) +
600
2.5 x t_CK
+t_AC(max.) +
1000
t_ANPD
3
-
3
-
t_AXPD
8
-
8
-
Unit Note
t_CK
ns
ns
ns
t_CK
ps
10
ps
t_CK 11,12
ps
ps
t_CK
t_CK
Note:
1. t_DAL[nCLK] = WR[nCLK] + tn_RP [nCLK] =WR+RU{t_RP[ps]/t_CK(avg)[ps]}, where WR is the value programmed in the mode
register set and RU status for round up.
2. AL: Additive Latency.
3. MRS A12 bit defines which Active Power-Down Exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH (AC) level for a rising
signal and VIL (AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIL (DC) level for a rising
signal and VIH (DC) for a falling signal applied to the device under test.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2013
Revision : 1.3
17/64