M14D1G1664A-2D Datasheet, PDF (6/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D1G1664A (2D)
DC Specifications
(IDD values are for the operation range of Voltage and Temperature)
Parameter
Symbol
Test Condition
Version
Unit
-1.8
-2.5
-3
One bank;
Operating Current
(Active - Precharge)
IDD0
t_CK = t_CK (IDD), t_RC = t_RC (IDD), t_RAS = t_RAS (IDD)min;
CKE is High, CS is HIGH between valid commands;
138
115
100
mA
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
One bank; I_OUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
Operating Current
t_CK = t_CK (IDD), t_RC = t_RC (IDD),
(Active - Read -
IDD1 t_RAS = t_RAS (IDD)min, t_RCD = t_RCD (IDD);
156
130
120
mA
Precharge)
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Precharge
Power-Down
Standby Current
IDD2P
All banks idle;
t_CK = t_CK (IDD); CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
10
10
10
mA
Precharge Quiet
Standby Current
IDD2Q
All banks idle;
t_CK = t_CK (IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
72
60
50
mA
All banks idle;
Idle Standby Current IDD2N
t_CK = t_CK (IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are SWITCHING;
78
65
50
mA
Data bus inputs are SWITCHING
Active Power-down
Standby Current
IDD3P
All banks open;
t_CK = t_CK (IDD); CKE is LOW;
Other control and address bus inputs
Fast PDN Exit
MRS(12) = 0
36
30
25
mA
are STABLE;
Data bus input are FLOATING
Slow PDN Exit
MRS(12) = 1
11
10
10
All banks open;
Active Standby
Current
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
IDD3N CKE is HIGH, CS is HIGH between valid commands;
90
Other control and address bus inputs are SWITCHING;
75
65
mA
Data bus inputs are SWITCHING
All banks open, continuous burst Reads, I_OUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0;
Operation Current
(Read)
IDD4R
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
CKE is HIGH, CS is HIGH between valid commands;
282
235
150
mA
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
All banks open, continuous burst Writes;
BL = 4, CL = CL (IDD), AL = 0;
Operation Current
(Write)
IDD4W
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
CKE is HIGH, CS is HIGH between valid commands;
282
235
150
mA
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2013
Revision : 1.3
6/64