M14D1G1664A-2D Datasheet, PDF (35/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D1G1664A (2D)
CLK
CLK
CKE
ODT
Internal
Term Res.
ODT Timing for Power-Down Mode
T0
T1
T2
T3
T4
T5
tIS
tAONPD(min.)
tAONPD(max.)
tIS
tAOFPD(min.)
Rtt
T6
tAOFPD(max.)
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2013
Revision : 1.3
35/64