M14D1G1664A-2D Datasheet, PDF (7/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D1G1664A (2D)
Parameter
Symbol
Test Condition
Version
Unit
-1.8
-2.5
-3
t_CK = t_CK (IDD);
Burst Auto Refresh
Current
Refresh command every t_RFC (IDD) interval;
IDD5B CKE is HIGH, CS is HIGH between valid commands; 252
210
200
mA
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
t_CK = t_CK (IDD);
Distributed Auto
Refresh Current
Refresh command every t_REFI interval;
IDD5D CKE is HIGH, CS is HIGH between valid commands; 16
15
15
mA
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self Refresh Mode;
Self Refresh Current
IDD6
CLK and CLK at 0V; CKE  0.2V;
Other control and address bus inputs are FLOATING;
9
mA
Data bus inputs are FLOATING
All bank interleaving Reads, I_OUT = 0mA;
BL = 4, CL= CL (IDD), AL = t_RCD (IDD) – 1 × t_CK (IDD);
t_CK = t_CK (IDD), t_RC = t_RC (IDD),
t_RRD = t_RRD (IDD), t_RCD = 1 × t_CK (IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are STABLE during Deslects;
Operating Current
(Bank interleaving)
IDD7
Timing pattern:
-DDR2-667 (5-5-5): A0 RA0 D D A1 RA1 D D A2 RA2
D D A3 RA3 D D D D D D
396
330
260
mA
-DDR2-800 (5-5-5): A0 RA0 D D A1 RA1 D D A2 RA2
D D A3 RA3 D D D D D D D D D
-DDR2-1066 (7-7-7): A0 RA0 D D D D A1 RA1 D D D
D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D
(Legend: A = Activate, RA = Read with Auto
Precharge, D = DESELECT)
Note:
1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS and DQS , IDD values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD:
LOW is defined as V_IN  V_IL (AC) (max.).
HIGH is defined as V_IN V_IH (AC) (min.).
STABLE is defined as inputs stable at a HIGH or LOW level.
FLOATING is defined as inputs at V_REF = V_DDQ/2
SWITCHING is defined as:
Address and control signal Inputs are changed between HIGH and LOW every other clock cycle (once per two clocks), and
DQ (not including mask or strobe) signal inputs are changed between HIGH and LOW every other data transfer (once per
clock).
6. When T_C ≧ +85 ℃, IDD6 must be derated by 80%.
IDD6 will increase by this amount if T_C ≧ +85 ℃ and double refresh option is still enabled.
7. AC Timing for IDD test conditions
For purposes of IDD testing, the following parameters are to be utilized.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2013
Revision : 1.3
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