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| M14D1G1664A-2D Datasheet, PDF (63/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle | |||
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ESMT
Revision History
Revision
1.0
1.1
1.2
1.3
Date
2012.03.12
2012.03.21
2012.07.26
2013.08.29
M14D1G1664A (2D)
Description
Original
Correct Product ID
Correct the specification of tCK for speed grade -1.8
Correct typo
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2013
Revision : 1.3
63/64
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