M14D1G1664A-2D Datasheet, PDF (11/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D1G1664A (2D)
AC Operating Test Conditions
Parameter
Value
Unit
Note
Input reference voltage ( V_REF )
Input signal maximum peak swing ( V_SWING(max.) )
Input signal minimum slew rate
0.5 x V_DDQ
1.0
1.0
V
5,1
V
5,1
V/ns
2,3
Input level
V_IH / V_IL
V
Input timing measurement reference level
V_REF
V
Output timing measurement reference level (V_OTR)
0.5 x V_DDQ
V
4
Note:
1. Input waveform timing is referenced to the input signal crossing through the V_REF level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from V_IL (DC)(max.) to V_IH (AC) (min.) for rising edges
and the range from V_IH (DC)(min.) to V_IL (AC)(max.) for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from V_IL (AC) to V_IH (AC) on the positive transitions and V_IH (AC) to
V_IL (AC) on the negative transitions.
4. The V_DDQ of the device under test is reference.
5. This timing and slew rate definition is valid for all single-ended signals except t_IS, t_IH, t_DS, and t_DH.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2013
Revision : 1.3
11/64