M14D1G1664A-2D Datasheet, PDF (12/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D1G1664A (2D)
AC Timing Parameter & Specifications
Parameter
Symbol
-1.8
Min.
Max.
CL=7
1875
8000
CL=6
2500
8000
Clock period
CL=5
t_CK (avg)
2500
8000
CL=4
3750
8000
CL=3
5000
8000
DQ output access time from
CLK/ CLK
t_AC
-350
+350
CLK high-level width
CLK low-level width
DQS output access time from
CLK/ CLK
t_CH (avg)
t_CL (avg)
t_DQSCK
0.48
0.48
-350
0.52
0.52
+350
Clock to first rising edge of DQS
delay
t_DQSS
-0.25
+0.25
Data-in and DM setup time
(to DQS)
t_DS
(base)
0
-
Data-in and DM hold time
(to DQS)
t_DH
(base)
75
-
DQ and DM input pulse width
(for each input)
t_DIPW
0.35
-
Address and Control Input
setup time
t_IS (base)
125
-
Address and Control Input hold
time
t_IH (base)
200
-
Control and Address input pulse
width
t_IPW
0.6
-
DQS input high pulse width
t_DQSH
0.35
-
DQS input low pulse width
t_DQSL
0.35
-
DQS falling edge to CLK rising
setup time
t_DSS
0.2
-
DQS falling edge from CLK
rising hold time
t_DSH
0.2
-
Data strobe edge to output data
edge
t_DQSQ
-
175
Data-out high-impedance
window from CLK/ CLK
t_HZ
-
t_AC(max.)
Data-out low-impedance window tLZ
from CLK/ CLK
(DQS)
t_AC(min.)
t_AC(max.)
DQ low-impedance window from
CLK/ CLK
Half clock period
t_LZ
(DQ)
t_HP
2 x t_AC(min.)
Min
(t_CL(abs),t_CH(abs))
t_AC(max.)
-
Elite Semiconductor Memory Technology Inc.
Unit Note
ps
ps
t_CK (avg)
t_CK (avg)
ps
t_CK (avg)
ps
4
ps
5
t_CK (avg)
ps
4
ps
5
t_CK (avg)
t_CK (avg)
t_CK (avg)
t_CK (avg)
t_CK (avg)
ps
ps
ps
ps
ps
6
Publication Date : Aug. 2013
Revision : 1.3
12/64