M14D1G1664A-2D Datasheet, PDF (29/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D1G1664A (2D)
Extended Mode Register Set-2 [EMRS(2)]
The EMRS(2) stores the data for enabling or disabling high temperature self refresh rate. The default value of the EMRS(2) is not
defined, therefore EMRS(2) must be written after power up for proper operation. The EMRS(2) is written by asserting LOW on CS ,
RAS , CAS , WE , BA0, BA2 and HIGH on BA1 (The device should be in all bank Precharge with CKE already high prior to
writing into EMRS(2)). The state of address pins A0~A12 in the same cycle as CS , RAS , CAS , WE , BA0 and BA2 going LOW
and BA1 going HIGH are written in the EMRS(2).
The t_MRD time is required to complete the write operation to the EMRS(2). The EMRS(2) contents can be changed using the same
command and clock cycle requirements during normal operation as long as all banks are in the idle state. A7 is used for high
temperature self refresh rate enable or disable.
BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
1
0
0^*1
SRF
0^*1
PASR^*2
BA2 BA1 BA0
000
001
010
011
Mode
Register
MRS
EMRS(1)
EMRS(2)
EMRS(3):
Reserved
A7
High Temperature
Self Refresh rate
0
Disable
1
Enable
A2 A1 A0
000
001
010
011
100
101
110
111
Partial Array Self Refresh
Full array
1/2 array (BA[2:0] = 000, 001,
010 & 011)
1/4 array (BA[2:0] = 000 & 001)
1/8 array (BA[2:0] = 000)
3/4 array (BA[2:0] = 010, 011,
100, 101, 110 &111)
1/2 array (BA[2:0] = 100, 101,
110 &111)
1/4 array (BA[2:0] = 110 &111)
1/8 array (BA[2:0] = 111)
*Note:
1. A3~A6 and A8~A12 are reserved for future use and must be set to 0.
2. Optional, if PASR (Partial Array Self Refresh) is enabled, data location in areas of the array beyond the spec. location
will be lost if self refresh is entered.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2013
Revision : 1.3
29/64