M14D1G1664A-2D Datasheet, PDF (14/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D1G1664A (2D)
AC Timing Parameter & Specifications - Contiuned
Parameter
Exit active power-down to Read
command
(slow exit / low power mode)
CKE minimum pulse width
(high and low pulse width)
Minimum time clocks remains
ON after CKE asynchronously
drops low
Output impedance test driver
delay
MRS command to ODT update
delay
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down
mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down
mode)
ODT to Power-Down entry
latency
ODT Power-Down exit latency
Symbol
t_XARDS
-1.8
Min.
Max.
10 - AL
-
t_CKE
3
-
t_DELAY t_IS + t_CK (avg)+t_IH
-
t_OIT
0
12
t_MOD
t_AOND
t_AON
t_AONPD
t_AOFD
t_AOF
t_AOFPD
t_ANPD
t_AXPD
0
12
2
2
t_AC(min.)
t_AC(max.) + 2575
t_AC(min.) + 2000
2 x t_CK +t_AC(max.)
+ 1000
2.5
2.5
t_AC(min.)
t_AC(max.) + 600
t_AC(min.) + 2000
2.5 x t_CK
+t_AC(max.) + 1000
2.5
-
11
-
Unit
t_CK
t_CK
ns
ns
ns
t_CK
ps
ps
t_CK
ps
ps
t_CK
t_CK
Note
2,3
10
11,12
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2013
Revision : 1.3
14/64