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M14D1G1664A-2D Datasheet, PDF (1/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle | |||
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ESMT
M14D1G1664A (2D)
DDR II SDRAM
8M x 16 Bit x 8 Banks
DDR II SDRAM
Features
ï¬ JEDEC Standard
ï¬ VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V
ï¬ Internal pipelined double-data-rate architecture; two data access per clock cycle
ï¬ Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.
ï¬ On-chip DLL
ï¬ Differential clock inputs (CLK and CLK )
ï¬ DLL aligns DQ and DQS transition with CLK transition
ï¬ 8 bank operation
ï¬ CAS Latency : 3, 4, 5, 6, 7
ï¬ Additive Latency: 0, 1, 2, 3, 4, 5
ï¬ Burst Type : Sequential and Interleave
ï¬ Burst Length : 4, 8
ï¬ All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
ï¬ Data I/O transitions on both edges of data strobe (DQS)
ï¬ DQS is edge-aligned with data for READ; center-aligned with data for WRITE
ï¬ Data mask (DM) for write masking only
ï¬ Off-Chip-Driver (OCD) impedance adjustment
ï¬ On-Die-Termination for better signal quality
ï¬ Special function support
- 50/ 75/ 150 ohm ODT
- High Temperature Self refresh rate enable
- Partial Array Self Refresh (PASR)
ï¬ Auto & Self refresh
ï¬ Refresh cycle :
- 8192 cycles/64ms (7.8μ s refresh interval) at 0 â ⦠TC ⦠+85 â
- 8192 cycles/32ms (3.9μ s refresh interval) at +85 â ï¼ TC ⦠+95 â
ï¬ SSTL_18 interface
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2013
Revision : 1.3
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