M14D1G1664A-2D Datasheet, PDF (19/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D1G1664A (2D)
ODT DC Electrical Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Unit
Rtt effective impedance value for 75Ω setting
EMRS(1) [A6, A2] = 0, 1
Rtt effective impedance value for 150Ω setting
EMRS(1) [A6, A2) = 1, 0
Rtt effective impedance value for 50Ω setting
EMRS(1) [A6, A2] = 1, 1
Deviation of VM with respect to V_DDQ /2
Rtt1(eff)
60
75
90
Ω
Rtt2(eff)
120
150
180
Ω
Rtt3(eff)
40
50
60
Ω
△VM
-6
-
+6
%
Note:
Measurement Definition for Rtt(eff) :
Rtt(eff) is determined by separately applying VIH(AC) and VIL(AC) to test pin, and then measuring current I(VIH(AC)) and
I(VIL(AC)) respectively.
Measurement Definition for △VM :
Measure voltage (VM) at test pin with no load.
OCD Default Characteristics
Parameter
Min.
Typ.
Max.
Unit
Note
Output impedance
12.6
18
23.4
Ω
1
Pull-up and pull-down mismatch
0
-
4
Ω
6
Output Impedance step size for
OCD calibration
0
-
1.5
Ω
1,2,3
Output slew rate
1.5
-
5
V/ns 1,4,5,7,8
Note:
1. Absolute specifications: the operation range of Voltage and Temperature.
2. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1,420mV; (VOUT - VDDQ)/IOH must be
less than 23.4Ω for values of VOUT between VDDQ and VDDQ - 280mV. Impedance measurement condition for output sink
DC current: VDDQ = 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4Ω for values of VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-down; both are measured at same temperature and voltage.
4. Slew rate measured from VIL (AC) to VIH (AC).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from
AC to AC. This is guaranteed by design and characterization.
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and
represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 ±
0.75 ohms under nominal conditions.
7. DRAM output slew rate specification applies to 533MT/s, 667MT/s, and 800MT/s speed pin.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQ’s is included in t_DQSQ and
t_QHS specification.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2013
Revision : 1.3
19/64